1. Field of the Invention
The present invention relates to an analog-to-digital conversion circuit configured to convert an input analog signal into a digital signal, and particularly to a parallel type analog-to-digital conversion circuit that achieves a smaller area and lower power consumption.
2. Description of the Related Art
FIG. 13 is a diagram showing an example of configuration of an ordinary parallel type analog-to-digital conversion circuit.
The analog-to-digital conversion circuit shown in FIG. 13 has a resistance ladder (R1 to R8) for generating a plurality of reference voltages, amplifier circuits A1 and A2 in two stages, master comparator latches U31 to U37 for performing comparison and determination, and an encoding circuit A3.
The amplifier circuits in the two stages amplify differences between the plurality of reference voltages generated by the resistance ladder (R1 to R8) and an analog input voltage. The master comparator latches U31 to U37 simultaneously perform comparing operation according to a clock signal CKA. Master comparator latches to which a reference voltage higher than the analog input voltage is input all generate an output having a “0” level, while master comparator latches to which a reference voltage lower than the analog input voltage is input all generate an output having a “1” level. The encoding circuit A3 performs a logical process of an exclusive disjunction of adjoining comparison outputs, converts a result of the process into a digital signal, and then outputs the digital signal. Since a sufficient gain may not-be obtained with amplifier circuits in one stage, about two amplification stages are provided in many cases.
As for example, Japanese Patent Laid-Open No. 2000-183742 relates to a parallel type analog-to-digital conversion circuit.